library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity vgaGenerator_v2 is
  port(clk50_in 		: in std_logic;
		 req_in			: in std_logic_vector(11 downto 0);
       red_out 	 	: out std_logic_vector(3 downto 0);
       green_out		: out std_logic_vector(3 downto 0);
       blue_out  		: out std_logic_vector(3 downto 0);
       hs_out    		: out std_logic;
       vs_out    		: out std_logic;
		 req_out			: out std_logic_vector(19 downto 0)
		 );
end vgaGenerator_v2;

architecture Behavioral of vgaGenerator_v2 is

signal clk25              : std_logic;
signal horizontal_counter : std_logic_vector (9 downto 0);
signal vertical_counter   : std_logic_vector (9 downto 0);

begin

-- generate a 25Mhz clock (pixel clock)
process (clk50_in)
begin
  if rising_edge(clk50_in) then
    clk25 <= NOT(clk25);
  end if;
end process;

process (clk25) 
begin
 
   if rising_edge(clk25) then
		
		--checks if setup times has passed
		--horizontal > Back Porch (48px) + Sync Pulse (96px) && < Back Porch (48px) + Sync Pulse (96px) + 640px
		--vertical > && < 480px
		 if (horizontal_counter >= "0010010000" ) -- 144
		 and (horizontal_counter < "1100010000" ) -- 784
		 and (vertical_counter >= "0000100111" ) -- 39
		 and (vertical_counter < "1000000111" ) -- 519
		 then
			-- R"XXXX"(11..8) G"XXXX" B"XXXX"
			--SET TO INPUT
			red_out <= req_in(11 downto 8);
			green_out <= req_in(7 downto 4);
			blue_out <= req_in(3 downto 0);
			
		else
		
			--during setup, set RGB to 0
			red_out <= conv_std_logic_vector(0,4);
			green_out <= conv_std_logic_vector(0,4);
			blue_out <= conv_std_logic_vector(0,4);
		end if;

		if (horizontal_counter > "0000000000" )
			and (horizontal_counter < "0001100001" ) -- 96+1
		then
			--Horizontal Sync Pulse, new pixel
			hs_out <= '0';
		else
			--Horizontal Sync Pulse = 1 when passing pixelcolors
			hs_out <= '1';
		end if;
		 
		if (vertical_counter > "0000000000" )
			and (vertical_counter < "0000000011" ) -- 2+1
		then
			--Vertical Sync Pulse, new row
			vs_out <= '0';
		else
			--Vertical Sync Pulse = 1 when passing pixelcolors
			vs_out <= '1';
		end if;

		--inclements horizontal_counter to keep track of horizontal position
		horizontal_counter <= horizontal_counter+"0000000001";
		
		if (horizontal_counter="1100100000") then --800 => Back Porch (48px) + Sync Pulse (96px) + 640px + Front Porch(16px)
			--if endline inclement Verical position, reset Horizontal position
			vertical_counter <= vertical_counter+"0000000001";
			horizontal_counter <= "0000000000";
		end if;
		 
		if (vertical_counter="1000001001") then --521
			--if endscreeen reset Verical position
			vertical_counter <= "0000000000";
		end if;
		
		req_out <= (horizontal_counter-"0010010000")&(vertical_counter-"0000100111");
	 
	end if; -- CLK25
end process;

end Behavioral;